SY100EL34LZITR 데이터 시트보기 (PDF) - Micrel

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SY100EL34LZITR

5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP

Micrel 

Micrel, Inc.

TIMING DIAGRAM

Precision Edge®

SY10EL34/L

SY100EL34/L

Internal Clock

Disabled

Internal Clock

Enabled

CLK

Q0

Q1

Q2

EN

The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers

will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs

will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.

M9999-031006

hbwhelp@micrel.com or (408) 955-1690

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