MAX16903SATB 데이터 시트보기 (PDF) - Maxim Integrated

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MAX16903SATB

2.1MHz, High-Voltage, 1A Mini-Buck Converter

Maxim Integrated 

MAX16903

2.1MHz, High-Voltage,

1A Mini-Buck Converter

value lowers the peak-to-average current ratio yielding a

lower input capacitance requirement.

The input ripple comprises mainly of ΔVQ (caused by the

capacitor discharge) and ΔVESR (caused by the ESR of

the input capacitor). The total voltage ripple is the sum of

ΔVQ and ΔVESR. Assume the input-voltage ripple from

the ESR and the capacitor discharge is equal to 50%

each. The following equations show the ESR and capaci-

tor requirement for a target voltage ripple at the input:

ESR

=

∆VESR

IOUT

+

∆IP−P

2





CIN

=

IOUT × D(1− D)

∆VQ × fSW

where:

∆IP−P

= (VIN − VOUT )× VOUT

VIN ×fSW ×L

and:

D = VOUT

VIN

where IOUT is the output current, D is the duty cycle,

and fSW is the switching frequency. Use additional input

capacitance at lower input voltages to avoid possible

undershoot below the UVLO threshold during transient

loading.

Output Capacitor

To maintain acceptable phase margin, a minimum ceramic

output capacitor value of 10μF is needed with a voltage

rating 2 times the VOUT voltage. Additional output capaci-

tance may be needed based on application-specific output-

voltage ripple requirements.

The allowable output-voltage ripple and the maximum

deviation of the output voltage during step load currents

determine the output capacitance and its ESR. The out-

put ripple comprises of ΔVQ (caused by the capacitor

discharge) and ΔVESR (caused by the ESR of the output

capacitor). Use low-ESR ceramic or aluminum electrolytic

capacitors at the output. For aluminum electrolytic capaci-

tors, the entire output ripple is contributed by ΔVESR. Use

the ESROUT equation to calculate the ESR requirement

and choose the capacitor accordingly. If using ceramic

capacitors, assume the contribution to the output ripple

voltage from the ESR and the capacitor discharge to be

equal. The following equations show the output capaci-

tance and ESR requirement for a specified output-voltage

ripple.

ESR = ∆VESR

∆IP−P

C OUT

=

8

×

∆IP−P

∆VQ × fSW

where:

∆IP−P

= (VIN − VOUT ) × VOUT

VIN ×fSW ×L

VOUT_RIPPLE ≅ ∆VESR + ∆VQ

ΔIP-P is the peak-to-peak inductor current as calculated

above and fSW is the converter’s switching frequency.

The allowable deviation of the output voltage during fast

transient loads also determines the output capacitance

and its ESR. The output capacitor supplies the step

load current until the converter responds with a greater

duty cycle. The response time (tRESPONSE) depends

on the closed-loop bandwidth of the converter. The high

switching frequency of the MAX16903 allows for a higher

closed-loop bandwidth, thus reducing tRESPONSE and

the output capacitance requirement. The resistive drop

across the output capacitor’s ESR and the capacitor dis-

charge causes a voltage droop during a step load. Use a

combination of low-ESR tantalum and ceramic capacitors

for better transient load and ripple/noise performance.

Keep the maximum output-voltage deviations below the

tolerable limits of the electronics being powered. When

using a ceramic capacitor, assume an 80% and 20%

contribution from the output capacitance discharge and

the ESR drop, respectively. Use the following equations to

calculate the required ESR and capacitance value:

ESR OUT

=

∆VESR

ISTEP

C OUT

=

ISTEP ×

t RESPONSE

∆VQ

where ISTEP is the load step and tRESPONSE is the

response time of the converter. The converter response

time depends on the control-loop bandwidth.

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