MAX16936(2018) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX16936
(Rev.:2018)

36V, 220kHz to 2.2MHz Step-Down Converters with 28µA Quiescent Current

Maxim Integrated 

MAX16936/MAX16938

36V, 220kHz to 2.2MHz Step-Down Converters

with 28µA Quiescent Current

OUT

COMP

PGOOD

EN

SUP BIAS

FB

FBSW

FBOK

AON

HVLDO

SWITCH

OVER

EAMP

REF

SOFT

START

PWM

LOGIC

HSD

CS

BIAS

BST

SUPSW

LX

MAX16936

MAX16938

SLOPE

COMP

LSD

OSC

PGND

SYNCOUT

Figure 1. Internal Block Diagram

FSYNC FOSC AGND

Linear Regulator Output (BIAS)

The devices include a 5V linear regulator (BIAS) that

provides power to the internal circuit blocks. Connect a

1FF ceramic capacitor from BIAS to AGND. When the

output voltage is set between 3V and 5.5V, the internal

linear regulator only provides power until the output is in

regulation. The internal linear regulator turns off once the

output is in regulation and allows OUT to provide power

to the device. The internal regulator turns back on once

the external load on the output of the device is higher than

100mA. In addition, the linear regulator turns on anytime

the output voltage is outside the 3V to 5.5V range.

Power-Good Output (PGOOD)

The devices feature an open-drain power-good output,

PGOOD. PGOOD asserts when VOUT rises above 95% of

its regulation voltage. PGOOD deasserts when VOUT drops

below 92% of its regulation voltage. Connect PGOOD to

BIAS with a 10kI resistor.

Overvoltage Protection (OVP)

If the output voltage reaches the OVP threshold, the high-

side switch is forced off and the low-side switch is forced

on until negative-current limit is reached. After negative-

current limit is reached, both the high-side and low-side

switches are turned off. The MAX16938 offers a lower

voltage threshold for applications requiring tighter limits

of protection.

Synchronization Input (FSYNC)

FSYNC is a logic-level input useful for operating mode

selection and frequency control. Connecting FSYNC to

BIAS or to an external clock enables fixed-frequency

FPWM operation. Connecting FSYNC to AGND enables

skip mode operation.

The external clock frequency at FSYNC can be higher or

lower than the internal clock by 20%. Ensure the duty cycle

of the external clock used has a minimum pulse width of

100ns. The device synchronizes to the external clock within

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