MAX19527 데이터 시트보기 (PDF) - Maxim Integrated

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MAX19527

Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs

Maxim Integrated 

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

Pin Description (continued)

PIN

NAME

FUNCTION

G1

IN5-

Channel 5 Negative (Inverting) Analog Input

G2

IN5+

Channel 5 Positive (Noninverting) Analog Input

H1

IN6-

Channel 6 Negative (Inverting) Analog Input

H2

IN6+

Channel 6 Positive (Noninverting) Analog Input

J1

IN7-

Channel 7 Negative (Inverting) Analog Input

J2

IN7+

Channel 7 Positive (Noninverting) Analog Input

K1

IN8-

Channel 8 Negative (Inverting) Analog Input

K2

IN8+

Channel 8 Positive (Noninverting) Analog Input

L8

CLKIN+ Clock Positive (Noninverting) Input

M8

CLKIN-

Clock Negative (Inverting) Input. If CLKIN- is connected to ground, CLKIN+ is a single-ended,

logic-level clock input. Otherwise, CLKIN+ and CLKIN- are self-biased differential clock inputs.

LVDS OUTPUTS

B11

OUT1+ Channel 1 Positive (Noninverting) LVDS Digital Output

B12

OUT1- Channel 1 Negative (Inverting) LVDS Digital Output

C11

OUT2+ Channel 2 Positive (Noninverting) LVDS Digital Output

C12

OUT2- Channel 2 Negative (Inverting) LVDS Digital Output

D11

OUT3+ Channel 3 Positive (Noninverting) LVDS Digital Output

D12

OUT3- Channel 3 Negative (Inverting) LVDS Digital Output

E11

OUT4+ Channel 4 Positive (Noninverting) LVDS Digital Output

E12

OUT4- Channel 4 Negative (Inverting) LVDS Digital Output

F11

CLKOUT+ Positive (Noninverting) Serial LVDS Clock Output

F12

CLKOUT- Negative (Inverting) Serial LVDS Clock Output

G11

FRAME+

Positive (Noninverting) Frame-Alignment LVDS Output. A rising edge on the differential FRAME

output aligns to a valid output data frame.

G12

FRAME-

Negative (Inverting) Frame-Alignment LVDS Output. A rising edge on the differential FRAME output

aligns to a valid output data frame.

H11

OUT5+ Channel 5 Positive (Noninverting) LVDS Digital Output

H12

OUT5- Channel 5 Negative (Inverting) LVDS Digital Output

J11

OUT6+ Channel 6 Positive (Noninverting) LVDS Digital Output

J12

OUT6- Channel 6 Negative (Inverting) LVDS Digital Output

K11

OUT7+ Channel 7 Positive (Noninverting) LVDS Digital Output

K12

OUT7- Channel 7 Negative (Inverting) LVDS Digital Output

L11

OUT8+ Channel 8 Positive (Noninverting) LVDS Digital Output

L12

OUT8- Channel 8 Negative (Inverting) LVDS Digital Output

3-WIRE SERIAL PERIPHERAL INTERFACE (SPI)

L10

SDIO

SPI Data Input/Output

M10

SCLK

SPI Clock

M11

CS

SPI Chip Select

10

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