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MAX2116(2005) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX2116 Datasheet PDF : 15 Pages
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Complete DBS Direct-Conversion Tuner ICs
with Monolithic VCOs
Pin Description
PIN
NAME
FUNCTION
1, 2
IDC-, IDC+
I-Channel Baseband DC Offset Correction. Connect a 0.1µF ceramic chip capacitor from IDC-
to IDC+.
3
VCCRF1
DC Power Supply for LNA and First-Stage RF VGA. Connect to a 5V ±5% low-noise supply.
Bypass with a 1nF capacitor directly to GND. Do not share vias.
4
RFIN-
75RF-Inverting Input. Working in conjunction with RFIN+ for differential input. Terminate with
22pF capacitor in series with a 75resistor to GND for single-ended input.
5
RFIN+
75RF Noninverting Input. Working in conjunction with RFIN- for differential input. Connect to
source through a 22pF series capacitor.
6, 9, 11, 25,
31
N.C.
No Connection. Pin should be connected directly to GND.
7
GC1
Gain Control Input for RF Front End. High-impedance analog input with an operating range of
0.75V to 2.6V. VGC1 = 0.75V corresponds to maximum gain.
8, 28
VREG1, VREG2
2.85V Linear Regulator. Used for terminating open-drain interfaces from demodulator. Each
regulator can source 3mA.
10
PAD
Ground. Direct connection to exposed pad. Can be used to check exposed pad continuity to
ground.
12
VCCLO
DC Power Supply for LO Circuits. Connect to a 5V ±5% low-noise supply. Bypass with a 1nF
capacitor directly to GND. Do not share vias.
13
14
15, 26, 32
16
17
18
19
VCCVCO
LOFLT
AS2, AS1, AS0
VTUNE
CPOUT
IFLT
VCCCPX
DC Power Supply for VCO Circuits. Connect to a 5V ±5% low-noise supply. See the
Applications Information section for more details.
LO Internal Regulator Bypass. Bypass with a 0.22µF ceramic chip capacitor to GND.
I2C Address Select Control. See Table 1 and Table 2. These pins are internally pullup
to VCC. For logic high, leave these pins open.
High Impedance VCO Tune Input
Charge-Pump Output
Test Pin. For normal operation, connect IFLT to ground.
DC Power Supply for Charge Pump and XTAL Oscillator Circuits. Connect to a 5V ±5% low-
noise supply. Bypass with a 1nF capacitor directly to GND. Do not share vias.
20
21, 22
23
24
27, 29
30
33
CFLT
Bypass for Internal Crystal Oscillator Bias. Bypass with a 0.22uF ceramic chip capacitor to
GND.
XTL+, XTAL- Crystal Oscillator Interface. See Typical Operating Circuit.
CNTOUT
Test Pin. Must be left open.
XTALOUT
SDA, SCL
Crystal Oscillator Buffer Output. Requires a 10nF DC-blocking capacitor.
I2C Data and Clock Interface. See the Applications Information section for details.
VCCDIG
DC Power Supply for Digital Circuits. Connect to a 5V ±5% low-noise supply. Bypass with a 1nF
capacitor directly to GND. Do not share vias.
N.C. (MAX2116) No Connection. Pin should be connected directly to GND.
QOUT- (MAX2118) Inverting Baseband Quadrature Output
_______________________________________________________________________________________ 9

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