MAX3420E 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3420E

USB Peripheral Controller with SPI Interface

Maxim Integrated 

MAX3420E

USB Peripheral Controller with SPI Interface

Pin Description (continued)

PIN

TQFN-EP TQFN-EP

NAME

INPUT/

OUTPUT

FUNCTION

SPI Serial-Data Output (Master-In, Slave-Out). MISO is a push-pull output. MISO

10

13

MISO

Output is three-stated in half-duplex mode or when SS = 1. The MISO logic level is

referenced to the voltage on VL.

Input or SPI Serial-Data Input (Master-Out, Slave-In). The logic level on MOSI is

11

14

MOSI

Input/ referenced to the voltage on VL. MOSI can also be configured as a bidirectional

Output MOSI/MISO input and output.

General-Purpose Multiplexed Output. The internal MAX3420E signal that

12

15

GPX

Output

Appears on GPX is programmable by writing to the GPXB and GPXA bits of the

PINCTL (R17) register. GPX indicates one of four signals: OPERATE (00,

default), VBUS_DET (01), BUSACT (10), and SOF (11).

Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage

13

17

INT

Output

on VL. In edge mode, INT is a push-pull output with programmable polarity. In

level mode, INT is open-drain and active low. Set the IE bit in the CPUCTL

(R16) register to enable INT.

15

20

D-

Input/ USB D- Signal. Connect D- to a USB “B” connector through a 33W ±1% series

Output resistor.

16

21

D+

Input/ USB D+ Signal. Connect D+ to a USB “B” connector through a 33W ±1% series

Output resistor. The 1.5kW D+ pullup resistor is internal to the device.

USB Transceiver Power-Supply Input. Connect VCC to a positive 3.3V power

17

22, 23

VCC

Input supply. Bypass VCC to ground with a 1.0µF ceramic capacitor as close to the

VCC pin as possible.

VBUS Comparator Input. VBCOMP is internally connected to a voltage

18

24

VBCOMP

Input

comparator to allow the SPI master to detect (through an interrupt or checking a

register bit) the presence or loss of power on VBUS. Bypass VBCOMP to ground

with a 1.0µF ceramic capacitor.

Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz

19

26

XI

Input ±0.25% crystal and a capacitor to GND. XI can also be driven by an external

Clock referenced to VCC.

Crystal Oscillator Output. Connect XO to the other side of a parallel resonant

20

27

XO

Output 12MHz ±0.25% crystal and a capacitor to GND. Leave XO unconnected if XI is

driven with an external source.

21

29

GPIN0

General-Purpose Inputs. GPIN3–GPIN0 are connected to VL with internal pullup

22

23

30

31

GPIN1

GPIN2

Input

resistors. GPIN3–GPIN0 logic levels are referenced to the voltage on VL. The

SPI master samples GPIN3–GPIN0 states by reading bit 7 through bit 4 of the

24

32

GPIN3

IOPINS (R20) register. Writing to these bits has no effect.

—

9, 16, 25,

28

N.C.

— No Internal Connection

—

—

EP

Input Exposed Paddle (TQFN only). Connect EP to GND.

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