MAX3420E 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3420E

USB Peripheral Controller with SPI Interface

Maxim Integrated 

MAX3420E

USB Peripheral Controller with SPI Interface

Register Description

The SPI master controls the MAX3420E by reading and

writing 21 registers (Table 1). For a complete description

of register contents, please refer to the “MAX3420E

Programming Guide.” A register access consists of the

SPI master first writing an SPI command byte, followed

by reading or writing the contents of the addressed

register. All SPI transfers are MSB first. The command

byte contains the register address, a direction bit (read

= 0, write = 1), and the ACKSTAT bit (Figure 4). The

SPI master addresses the MAX3420E registers by writing

the binary value of the register number in the Reg4

through Reg0 bits of the command byte. For example,

to access the IOPINS (R20) register, the Reg4 through

Reg0 bits would be as follows: Reg4 = 1, Reg3 = 0,

Reg2 = 1, Reg1 = 0, Reg0 = 0. The DIR (direction) bit

determines the direction for the data transfer. DIR = 1

means the data byte(s) will be written to the register,

and DIR = 0 means the data byte(s) will be read from

the register. The ACKSTAT bit sets the ACKSTAT bit in

the EPSTALLS (R9) register. The SPI master sets this

bit to indicate that it has finished servicing a CONTROL

transfer. Since the bit is frequently used, having it in the

SPI command byte improves firmware efficiency. In SPI

full-duplex mode, the MAX3420E clocks out eight USB

status bits as the command byte is clocked in (Figure 5).

In half-duplex mode, these status bits are accessed

in the normal way, as register bits.

b7

b6

b5

b4

b3

b2

Reg4

Reg3

Reg2

Reg1

Reg0

0

Figure 4. SPI Command Byte

b1

b0

DIR

ACKSTAT

b7

b6

b5

b4

b3

b2

b1

SUSPIRQ

URESIRQ SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ

Figure 5. USB Status Bits Clocked Out as First Byte of Every Transfer (Full-Duplex Mode Only)

b0

IN0BAVIRQ

The first five registers (R0–R4) access endpoint FIFOs.

To access a FIFO, an initial command byte sets the regis-

ter address and then consecutive reads or writes keep the

same register address to access subsequent FIFO bytes.

The remaining registers (R5–R20) control the operation

of the MAX3420E. Once a register address above R4

is set in the command byte, successive byte reads or

writes in the same SPI access cycle (SS low) increment

the register address after every byte read or written. This

incrementing operation continues until R20 is accessed.

Subsequent byte reads or writes continue to access R20.

Note that this autoincrementing action stops with the next

SPI cycle, which establishes a new register address.

Addressing beyond R20 is ignored.

The MAX3420E register map is depicted in Table 1. For a

complete description of all register contents, please refer

to the MAX3420E Programming Guide.

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