MAX3679 데이터 시트보기 (PDF) - Maxim Integrated

부품명

상세내역

제조사

MAX3679

+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

Maxim Integrated 

+3.3V, Low-Jitter Crystal to LVPECL

Clock Generator

Interfacing with LVPECL Outputs

The equivalent LVPECL output circuit is given in Figure 8.

These outputs are designed to drive a pair of 50Ω trans-

mission lines terminated with 50Ω to VTT = VCC - 2V. If a

separate termination voltage (VTT) is not available, other

+3.3V

termination methods can be used such as shown in

Figures 5 and 6. Unused outputs should be disabled and

can be left open. For more information on LVPECL termi-

nations and how to interface with other logic families,

refer to Application Note 291: HFAN-01.0: Introduction to

LVDS, PECL, and CML.

Interface Models

Figures 7, 8, and 9 show examples of interface models.

130Ω

130Ω

MAX3679 Qx

Z0 = 50Ω

HIGH

VCC

Qx

Z0 = 50Ω

IMPEDANCE

82Ω

82Ω

Qx

Figure 5. Thevenin Equivalent of Standard PECL Termination

Qx

MAX3679

Qx

0.1μF

Z0 = 50Ω

0.1μF

100Ω

Z0 = 50Ω

150Ω 150Ω

HIGH

IMPEDANCE

NOTE: AC-COUPLING IS OPTIONAL.

Figure 6. AC-Coupled PECL Termination

VCC

VB = 1.4V

VCC

VB

REF_IN

14.5kΩ

VB

Qx

ESD

STRUCTURES

Figure 8. Simplified LVPECL Output Circuit Schematic

DISABLE

IN

VDDO_A

10Ω

QA_C

10Ω

ESD

STRUCTURES

ESD

STRUCTURES

Figure 7. Simplified REF_IN Pin Circuit Schematic

Figure 9. Simplified LVCMOS Output Circuit Schematic

_______________________________________________________________________________________ 9

Share Link: