MAX3629 데이터 시트보기 (PDF) - Maxim Integrated
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MAX3629 Datasheet PDF : 12 Pages
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+3.3V, Low-Jitter, Precision Clock Generator
with Multiple Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is
bypassed, PLL_BP = low.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
INPUT SPECIFICATIONS (FSELA, FSELB, PLL_BP Pins)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input High Current
IIH
VIN = VDD
Input Low Current
IIL
VIN = 0V
LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6)
Input Clock Frequency
PLL enabled
PLL bypassed
Input Amplitude Range
(Note 7)
Input High Current
Input Low Current
Reference Clock Duty Cycle
IIH
VIN = VDD
IIL
VIN = 0V
Input Capacitance
CIN
CLOCK OUTPUT AC SPECIFICATIONS
VCO Center Frequency
Output Frequency with PLL
Enabled (Q0)
FSELA = GND
FSELA = VDD
FSELA = high-Z
Output Frequency with PLL
Enabled (Q1 to Q7)
FSELB = GND
FSELB = VDD
FSELB = high-Z (Note 8)
Output Frequency with PLL
Disabled
LVDS outputs
LVCMOS outputs
Integrated Phase Jitter at
125MH z/156.25MH z
RJRMS
12kHz to 20MHz, PLL_BP = high (Note 9)
12kHz to 20MHz, PLL_BP = high-Z
(Note 10)
Power-Supply Noise Rejection
(Note 11)
LVDS output
LVCMOS output
Deterministic Jitter Due to
Supply Noise (Note 12)
LVDS output
LVCMOS output
Nonharmonic and Subharmonic
Spurs
(Note 13)
f = 100Hz
f = 1kHz
LVDS Clock Output SSB Phase
Noise at 125MHz (Note 14)
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
MIN TYP MAX UNITS
2.0
VDD
V
0
0.8
V
80
μA
-80
μA
25
MHz
20
320
1.2
3.6
V
80
μA
-80
μA
40
50
60
%
1.5
pF
625
MHz
125
156.25
MHz
312.5
125
156.25
MHz
312.5
20
320
MHz
20
160
0.4
psRMS
0.4
-55
dBc
-47
9
psP-P
23
-73
dBc
-116
-124
-127
-131
-144
-149
dBc/H z
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