0.8Ω, Low-Voltage, Single-Supply, Dual SPDT
Analog Switch
Test Circuits/Timing Diagrams (continued)
MAX4736
VIN
LOGIC
INPUT
V+
NC_ or NO_
NO_ or NC_
V+
COM_
IN_
GND
VOUT
RL
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval
VIH + 0.5V
LOGIC
50%
INPUT
0
tr < 5ns
tf < 5ns
VOUT
0.9 ✕ VOUT
tD
MAX4736
VGEN
RGEN NC_
OR NO_
GND
V+
V+
COM_
IN
VOUT
CL
VINL TO VINH
Figure 3. Charge Injection
CAPACITANCE
METER
f = 1MHz
10nF V+
V+
COM_
MAX4736
NC_ OR
NO_
GND
IN_ VINL
OR
VINH
Figure 4. Channel Off/On-Capacitance
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Chip Information
TRANSISTOR COUNT: 379
PROCESS: CMOS
8 _______________________________________________________________________________________