MAX6323(2003) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX6323
(Rev.:2003)

µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset

Maxim Integrated 

µP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

+3.3V

VCC

MAX6324

RESET

GND

+5.0V

RPULLUP

VCC

5V SYSTEM

RESET

INPUT

GND

START

SET WDI

LOW

SUBROUTINE OR

PROGRAM LOOP

SET WDI HIGH

Figure 8. MAX6324 Open-Drain RESET Output Allows Use with

Multiple Supplies

drive the µP RESET input (Figure 10). The short 1ms

WDPO pulse output will assert the manual reset input

and force the RESET output to assert for the full reset

timeout period (100ms min). All internal RAM data is

lost during the reset period, but the processor is guar-

anteed to begin in the proper operating state.

MAX6323AUT29

MAX6323AUT46

MAX6323CUT29

MAX6323CUT46

MAX6323DUT29

MAX6323DUT46

MAX6323HUT29

MAX6323HUT46

Standard Versions

MAX6324AUT29

MAX6324AUT46

MAX6324BUT29

MAX6324BUT46

MAX6324EUT29

MAX6324EUT46

MAX6324HUT29

MAX6324HUT46

RETURN

END

Figure 9. Watchdog Flow Diagram

SUFFIX

46

44

31

29

26

23

Reset Threshold Range

(-40°C to +125°C)

MIN

TYP

MAX

UNITS

4.50

4.63

4.75

4.25

4.38

4.50

3.00

3.08

3.15

V

2.85

2.93

3.00

2.55

2.63

2.70

2.25

2.32

2.38

Chip Information

TRANSISTOR COUNT: 1371

PROCESS: BiCMOS

10 ______________________________________________________________________________________

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