MAX6323(2003) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX6323
(Rev.:2003)

µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset

Maxim Integrated 

µP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

VCC

VCC

MAX6323

RESET

R1

GND

100k

VCC

VCC

MAX6324

RESET

GND

VCC

µP

RESET

INPUT

GND

Figure 6. RESET Valid to VCC = Ground Circuit

Figure 7. Interfacing to µPs with Bidirectional Reset Pins

Interfacing to µPs with

Bidirectional Reset Pins

Since the RESET output on the MAX6324 is open-drain,

this device easily interfaces with µPs that have bidirec-

tional reset pins, such as the Motorola 68HC11.

Connecting the µP supervisor’s RESET output directly

to the microcontroller’s (µC’s) RESET pin with a single

pullup resistor allows either device to assert reset

(Figure 7).

MAX6324 Open-Drain RESET Output

Allows Use with Multiple Supplies

Generally, the pullup resistor connected to the

MAX6324 will connect to the supply voltage that is

being monitored at the IC’s VCC pin. However, some

systems may use the open-drain output to level-shift

from the monitored supply to reset circuitry powered by

some other supply (Figure 8). Keep in mind that as the

MAX6324’s VCC decreases below +1.2V, so does the

IC’s ability to sink current at RESET. Also, with any pull-

up resistor, RESET will be pulled high as VCC decays

toward 0. The voltage where this occurs depends on

the pullup resistor value and the voltage to which it is

connected.

Watchdog Software Considerations

To help the watchdog timer monitor software execution

more closely, set and reset the watchdog input at dif-

ferent points in the program, rather than “pulsing” the

watchdog input high-low-high or low-high-low. This

technique avoids a “stuck” loop in which the watchdog

time would continue to be reset within the loop, keeping

the watchdog from timing out.

Figure 9 shows an example of a flow diagram where

the I/O driving the watchdog input is set high at the

beginning of the program, set low at the beginning of

every subroutine or loop, then set high again when the

program returns to the beginning. If the program should

“hang” in any subroutine, the problem would be quickly

corrected, since the I/O is continually set low and the

watchdog time is allowed to time out, causing a reset or

interrupt to be issued.

WDPO to MR Loopback

An error detected by the watchdog often indicates that

a problem has occurred in the µP code execution. This

could be a stalled instruction or a loop from which the

processor cannot free itself. If the µP will still respond to

a nonmaskable input (NMI), the processor can be redi-

rected to the proper code sequence by connecting the

WDPO output to an NMI input. Internal RAM data

should not be lost, but it may have been contaminated

by the same error that caused the watchdog to time

out.

If the processor will not recognize NMI inputs, or if the

internal data is considered potentially corrupted when a

watchdog error occurs, the processor should be

restarted with a reset function. To obtain proper reset

timing characteristics, the WDPO output should be con-

nected to the MR input, and the RESET output should

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