MAX6951EEE 데이터 시트보기 (PDF) - Maxim Integrated
부품명
상세내역
제조사
MAX6951EEE Datasheet PDF : 19 Pages
| |||
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 10. Global Clear Digit Data (R Data Bit D5) Format
MODE
ADDRESS
REGISTER DATA
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Digit data for both
planes P0 and P1 are
unaffected
0x04
X
X
0
T
E
B
0
S
Digit data for both
planes P0 and P1 are
cleared on the rising
edge of CS
0x04
X
X
1
T
E
B
0
S
Table 11. Display-Test Register Format
MODE
Normal operation
Display test
ADDRESS
REGISTER DATA
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
0x07
X
X
X
X
X
X
X
0
0x07
X
X
X
X
X
X
X
1
Table 12. Scan-Limit Register Format
SCAN LIMIT
ADDRESS
REGISTER DATA
HEX
CODE (HEX) D7
D6
D5
D4
D3
D2
D1
D0 CODE
Display digit 0 only
0x03
X
X
X
X
X
0
0
0
0xX0
Display digits 0 and 1
0x03
X
X
X
X
X
0
0
1
0xX1
Display digits 0 and 1 2
0x03
X
X
X
X
X
0
1
0
0xX2
Display digits 0 and 1 2 3
0x03
X
X
X
X
X
0
1
1
0xX3
Display digits 0 and 1 2 3 4
0x03
X
X
X
X
X
1
0
0
0xX4
Display digits 0 and 1 2 3 4 5
0x03
X
X
X
X
X
1
0
1
0xX5
Display digits 0 and 1 2 3 4 5 6
0x03
X
X
X
X
X
1
1
0
0xX6
Display digits 0 and 1 2 3 4 5 6 7
0x03
X
X
X
X
X
1
1
1
0xX7
If the blink function is disabled through the Blink Enable
Bit E (Table 8) in the configuration register, then the digit
register data in plane P0 is used to multiplex the display.
The digit register data in P1 is not used (Table 17).
If the blink function is enabled, then the digit register
data in both plane P0 and plane P1 are alternately used
to multiplex the display. Blinking is achieved by multi-
plexing the LED display using data plane P0 and plane
P1 on alternate phases of the blink clock (Table 18).
Display Blink Mode
The display blinking facility, when enabled, makes the
driver flip automatically between displaying the digit
register data in planes P0 and plane P1. If the digit reg-
ister data for any individual segment is different in the
two planes, then that segment appears to blink or flash
on and off. Once blinking has been configured, it con-
tinues automatically without further intervention.
Blink Speed
The blink speed is determined by frequency of the mul-
tiplex clock, OSC, and by the setting of the Blink Rate
Selection Bit B (Table 7) in the configuration register.
The Blink Rate Selection Bit B sets either fast or slow
blink speed for the whole display.
Multiplex Clock and OSC Oscillator
The OSC input pin is used to set both the display scan
rate and the blink timing for the display driver. OSC
must either be fitted with an external capacitor CSET to
GND to set the frequency of the MAX6950/MAX6951s’
internal RC oscillator, or be overdriven with an external
TTL/CMOS clock.
______________________________________________________________________________________ 11
Share Link: 