MAX6951EEE 데이터 시트보기 (PDF) - Maxim Integrated
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MAX6951EEE Datasheet PDF : 19 Pages
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Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Slow Segment Blink Period
(Internal Oscillator)
fSLOWBLINK
Eight digits scanned, OSC = RC oscillator,
RSET = 56kΩ, CSET = 27pF
1
Fast Segment Blink Period
(Internal Oscillator)
fFASTBLINK
Eight digits scanned, OSC = RC oscillator,
RSET = 56kΩ, CSET = 27pF
0.5
Fast or Slow Segment Blink Duty
Cycle (Note 2)
49.9
50
Digit Drive Sink Current
Segment Drive Source Current
Digit Drive Sink Current (Note 2)
IDIGIT
TA = +25°C, VLED = 2.4V
240
320
ISEG
TA = +25°C, VLED = 2.4V
-30
-40
IDIGIT
TA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V
80
Segment Drive Source Current
(Note 2)
ISEG
TA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V
-10
Slew Rate Rise Time
∆ISEG/∆t TA = +25°C
35
LOGIC INPUTS
Input Current DIN, CLK, CS
IIH, IIL
VIN = 0 or V+
-2
Logic High Input Voltage DIN,
CLK, CS
VIH
2.4
Logic Low Input Voltage DIN,
CLK, CS
VIL
Hysteresis Voltage DIN, CLK, CS
∆VI
TIMING CHARACTERISTICS (Figure 1)
CLK Clock Period
tCP
CLK Pulse Width High
CLK Pulse Width Low
CS Fall to CLK Rise Setup Time
CLK Rise to CS Rise Hold Time
DIN Setup Time
tCH
tCL
tCSS
tCSH
tDS
DIN Hold Time
CS Pulse High
tDH
tCSW
TIMING CHARACTERISTICS (V+ = +2.7V) (Note 2)
CLK Clock Period
tCP
CLK Pulse Width High
tCH
CLK Pulse Width Low
CS Fall to CLK Rise Setup Time
CLK Rise to CS Rise Hold Time
DIN Setup Time
tCL
tCSS
tCSH
tDS
DIN Hold Time
CS Pulse High
tDH
tCSW
0.5
38.4
19
19
9.5
3
9.5
0
19
50
24
24
12
4
12
4
24
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
MAX UNITS
s
s
50.1
%
400
mA
-50
mA
mA
mA
mA/µs
2
µA
V
0.4
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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