MAX6953 데이터 시트보기 (PDF) - Maxim Integrated

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MAX6953

2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 ✕ 7 Matrix LED Display Driver

Maxim Integrated 

2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 ✕ 7

Matrix LED Display Driver

HOW COMMAND BYTE AND DATA BYTE MAP INTO

MAX6953'S REGISTERS

ACKNOWLEDGE FROM MAX6953

ACKNOWLEDGE FROM MAX6953

D15 D14 D13 D12 D11 D10 D9 D8

ACKNOWLEDGE FROM MAX6953

D7 D6 D5 D4 D3 D2 D1 D0

S

SLAVE ADDRESS

0A

COMMAND BYTE

A

DATA BYTE

AP

R/W

Figure 9. n Data Bytes Received

n BYTES

AUTOINCREMENT MEMORY WORD ADDRESS

digit appears to flip between two characters. To make a

character appear to blink on or off, write the character

to one plane, and use the blank character (0x20) for the

other plane. Once blinking has been configured, it con-

tinues automatically without further intervention.

Blink Speed

The blink speed is determined by frequency of the mul-

tiplex clock, OSC, and by setting the Blink Rate

Selection Bit B (Table 9) in the configuration register.

The Blink Rate Selection Bit B sets either fast or slow

blink speed for the whole display.

Initial Power-Up

On initial power-up, all control registers are reset, the

display is blanked, intensities are set to minimum, and

shutdown is enabled (Table 6).

Configuration Register

The configuration register is used to enter and exit shut-

down, select the blink rate, globally enable and disable

the blink function, globally clear the digit data, and

reset the blink timing (Table 7).

Shutdown Mode (S Data Bit D0) Format

The S bit in the configuration register selects shutdown

or normal operation. The display driver can be pro-

grammed while in shutdown mode, and shutdown mode

is overridden when in the display test mode. For normal

operation, the S bit should be set to 1 (Table 8).

Blink Rate Selection (B Data Bit D2) Format

The B bit in the configuration register selects the blink

rate. This is the speed that the segments alternate

between plane P0 and plane P1 refresh data. The blink

rate is determined by the frequency of the multiplex clock

OSC, in addition to the setting of the B bit (Table 9).

Table 3. MAX6953 Address Map

PIN

DEVICE ADDRESS

AD1 AD0 A6 A5 A4 A3 A2 A1 A0

GND GND 1 0 1 0 0 0 0

GND V+

1010001

GND SDA 1 0 1 0 0 1 0

GND SCL 1 0 1 0 0 1 1

V+ GND 1 0 1 0 1 0 0

V+

V+

1010101

V+ SDA 1 0 1 0 1 1 0

V+ SCL 1 0 1 0 1 1 1

SDA GND 1 0 1 1 0 0 0

SDA

V+

1011001

SDA SDA 1 0 1 1 0 1 0

SDA SCL 1 0 1 1 0 1 1

SCL GND 1 0 1 1 1 0 0

SCL

V+

1011101

SCL SDA 1 0 1 1 1 1 0

SCL SCL 1 0 1 1 1 1 1

10 ______________________________________________________________________________________

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