MAX8794(2006) 데이터 시트보기 (PDF) - Maxim Integrated
부품명
상세내역
제조사
MAX8794 Datasheet PDF : 13 Pages
| |||
Low-Voltage DDR Linear Regulator
Pin Description
PIN
NAME
FUNCTION
1
REFOUT Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
2
VCC
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or
greater ceramic capacitor.
3
AGND Analog Ground. Connect the backside pad to AGND.
4
REFIN
External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN).
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
5
PGOOD or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
6
OUTS
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ
resistor.
7
SHDN
Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the
linear regulator. The reference buffer remains active in shutdown.
8
PGND Power Ground. Internally connected to the output sink MOSFET.
9
OUT
Output of the Linear Regulator
10
IN
Power Input. Internally connected to the output source MOSFET.
_______________________________________________________________________________________ 7
Share Link: 