MAX9915 데이터 시트보기 (PDF) - Maxim Integrated

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MAX9915

1MHz, 20µA, Rail-to-Rail I/O Op Amps with Shutdown

Maxim Integrated 

1MHz, 20µA, Rail-to-Rail I/O Op Amps

with Shutdown

Power-Supply Considerations

The MAX9914–MAX9917 are optimized for single 1.8V

to 5.5V supply operation. A high amplifier power-supply

rejection ratio of 85dB (typ) allows the devices to be

powered directly from a battery, simplifying design and

extending battery life.

Power-Up Settling Time

The MAX9914–MAX9917 typically require 2µs after

power-up. Supply settling time depends on the supply

voltage, the value of the bypass capacitor, the output

impedance of the incoming supply, and any lead resis-

tance or inductance between components. Op amp

settling time depends primarily on the output voltage

and is slew-rate limited. Figure 3 shows the MAX991_ in

a noninverting voltage follower configuration with the

input held at midsupply. The output settles in approxi-

mately 3.5µs for VDD = 3V (see the Typical Operating

Characteristics for the Power-Up Settling Time graph).

Shutdown Mode

The MAX9915 and MAX9917 feature active-low shut-

down inputs. The MAX9915 and MAX9917 enter shut-

down in 2µs (typ) and exit shutdown in 10µs (typ). The

amplifiers’ outputs are high impedance in shutdown

mode. Drive SHDN low to enter shutdown. Drive SHDN

high to enable the amplifier. The MAX9917 dual amplifi-

er features separate shutdown inputs. Shut down both

amplifiers for lowest quiescent current.

Power-Supply Bypassing and Layout

Bypass VDD with a 0.1µF capacitor to ground as close

to the pin as possible to minimize noise.

Good layout techniques optimize performance by

decreasing the amount of stray capacitance and induc-

tance to the op amp’s inputs and outputs. Minimize

stray capacitance and inductance, by placing external

components close to the IC.

RAIL-TO-RAIL OUTPUT VOLTAGE RANGE

3V

IN_

1V/div

0V

3V

OUT_

1V/div

0V VDD = 3V

200µs/div

Figure 1. Rail-to-Rail Output Voltage Range

MAX9914–

MAX9917

RISO

RL

CL

AV =

RL

RL + RISO

≈ 1V/V

Figure 2. Using a Resistor to Isolate a Capacitive Load from

the Op Amp

5.5V

0V

IN-

VDD

100kΩ

MAX991_

OUT

IN+

VSS

100kΩ

Figure 3. Power-Up Test Configuration

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