MB15F05L 데이터 시트보기 (PDF) - Fujitsu
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MB15F05L Datasheet PDF : 24 Pages
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MB15F05L
s PIN DESCRIPTION
Pin No.
SSOP16 BCC16
1
16
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
Pin name I/O
Descriptions
GNDRF
OSCin
GNDIF
finIF
VccIF
LD/fout
PSIF
DoIF
DoRF
PSRF
XfinRF
VccRF
finRF
LE
Data
Clock
– Ground for RF–PLL section.
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
– Ground for the IF-PLL section.
I
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
– Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
O The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
LDS bit = ”L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
I
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode
PSIF = ”L” ; Power saving mode
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Power saving mode control for the RF-PLL section. This pin must be set
I
at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode
PSRF = ”L” ; Power saving mode
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the RF-PLL section, the shift register
– and the oscillator input buffer. When power is OFF, latched data of RF-
PLL is cancelled.
I
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
I
When LE is ”H”, data in the shift register is transferred to the
corresponding
latch according to the control bit in a serial data.
Serial data input (with the schmitt trigger circuit.)
I
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
I One bit data is shifted into the shift register on a rising edge of the
clock.
3
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