MB15F05L 데이터 시트보기 (PDF) - Fujitsu

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MB15F05L

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F05L

s BLOCK DIAGRAM

VccIF GNDIF

5

3

7

PSIF

finIF 4

Intermittent

mode

control

(IF–PLL)

Prescaler

(IF–PLL)

16/17

2

OSCin

OR

finRF 13

11

XfinRF

PSRF 10

Prescaler

(RF–PLL)

64/65,

128/129

Intermittent

mode

control

(RF–PLL)

Swallow counter Programmable

(IF–PLL)

counter(IF–PLL)

A=7

N = 291

fpIF

Phase

comp.

(IF–PLL)

Charge Super

pump charger

(IF–PLL)

8 DoIF

14bit latch

Reference

frIF

counter(IF–PLL)

(R=384)

Lock

Det.

(IF–PLL)

LDIF

frRF

Binary 14-bit pro-

T1 T2

grammable ref.

counter(RF–PLL)

2-bit latch

14-bit latch

AND

LDRF

Lock

Det.

(RF–PLL)

Selector

LD

frIF

frRF

fpIF

fpRF

6 LD/fout

LDS SWRF FCRF

3-bit latch

Binary 7-bit Binary 11-bit

swallow counter programmable

(RF–PLL)

counter(RF–PLL)

Phase

comp.

fpRF

7-bit latch

11-bit latch

Charge

pump

(RF–PLL)

Super

charger

9 DoRF

LE 14

Schmitt

circuit

Latch selector

Data 15

Clock 16

Schmitt

circuit

Schmitt

circuit

CC

NN

12

23-bit shift

register

Note: SSOP-16pin

12

VCCRF

1

GNDRF

4

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