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MB89P538PF-101 데이터 시트보기 (PDF) - Fujitsu

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MB89P538PF-101
Fujitsu
Fujitsu Fujitsu
MB89P538PF-101 Datasheet PDF : 56 Pages
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MB89530H Series
s PRODUCT LINEUP
Part number
Parameter
MB89537H/537HC
MB89538H/538HC
MB89P538
MB89PV530
Type
Mass produced (Mask ROM)
One-time
programmable
Evaluation
ROM capacity
32 K × 8-bit
(built-in ROM)
48 K × 8-bit
(built-in ROM)
48 K × 8-bit
(built-in ROM)
(write from general
purpose ERPOM writer)
48 K × 8-bit
(external ROM) *2
RAM capacity
1 K × 8-bit
2 K × 8-bit
Operating voltage
3.5 V to 5.5 V*1
(MB89537H/538H/537HC/538HC)
2.7 V to 5.5 V
CPU functions
Basic instructions
: 136
Instruction bit length
: 8-bits
Instruction length
: 1 bit to 3 bits
Data bit length
: 1, 8, 16-bits
Minimum instruction execution time : 0.32 µs / 12.5 MHz
Minimum interrupt processing time : 2.88 µs / 12.5 MHz
Ports
Input ports
: 5 (4 also usable as interrupts, 2 for sub clock)
Output-only ports (N-ch open drain)
: 8 (8 also usable as ADC input)
I/O ports (N-ch open drain) : 2 (2 also usable as SO2/SDA or SI2/SCL)
I/O ports (CMOS)
: 38 (21 have no other function)
Total
: 53
Time base timer
21 bits
Interrupt periods at main clock oscillation frequency of 12.5 MHz
(approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms)
Watchdog timer
Reset period of approx. 167.8 ms to 335.6 ms at mail clock frequency of 12.5 MHz
Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz.
PWM timer
8-bit interval timer operation*3
(supports square wave output, operating clock period : 1, 8, 16, 64 tinst*3)
Pulse width measurement with 8-bit resolution (conversion period : 28 tinst*3 to 28 × 64 tinst*3)
2 channels (can also be used as interval timer, can also be used as ch1 output and ch2
count clock)
Clock prescaler
Interval times at 17-bit sub clock base frequency of 32.768 kHz
(approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s)
(Continued)
3

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