MB91110 데이터 시트보기 (PDF) - Fujitsu

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MB91110

32-Bit RISC Microcontroller

Fujitsu 

MB91110 Series

(Continued)

• Branch instruction with delay slot : Reduction in overheads in case of branching

• Multiplier is built-in / Supported at instruction level

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

• Interruption (saving PC and PS) : 6 cycles, 16 priority levels

Bus Interface

• 24-bit address bus (16 MB space)

• Operating frequency : 25 MHz

• 16- / 8-bit data bus

• Basic external bus cycle : 2 clock cycles

• Chip select output that can be set to a minimum 64-Kbyte units

• Interface support for various memories

DRAM interface (areas 4, 5)

• Automatic waiting cycle : Can be randomly set from 0 to 7 cycles per area

• Unused data and address pins can be used as input/output ports.

• Supports “little endian” mode (One area is selected from areas 1 to 5)

DRAM Interface

• 2-bank individual control (area 4, 5)

• Normal mode / high speed page mode

• Basic bus cycles : normally 5 cycles, 1 cycle access is possible in high-speed page mode.

• Programmable waveform : 1 cycle waiting can be inserted automatically in RAS and CAS.

• DRAM refresh

CBR refresh (Interval is randomly set using the 6-bit timer.)

Self refresh mode

• Supports addresses for 8, 9, 10 and 12 columns

• 2CAS/1WE or 2WE/1CAS can be selected.

Cache Memory

• 1 KB instruction cache

• 2 way set associative

• 32 blocks / way, 4 entries (4 words) / block

• Lock function : Residing in the specified program codes at cache

DMA Controller (DMAC)

• 5 channels

• External → external 2.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)

• Internal → external 1.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)

• Address register (inc, dec, or reload are possible) : 32 bits × 5 channels

• Transfer count register (reload possible) : 16 bits × 5 channels

• Transfer factors : external pin / built-in resources interruption request / software

• Transfer sequence

Step transfer / block transfer

Burst / consecutive transfer

• Transfer data length : 8-bit, 16-bit or 32-bit can be selected

• Suspension is possible using NMI / interruption request

UART

• Fully duplicated double buffer

• Data length : 7 to 9 bits (without parity) , 6 to 8 bits (with parity)

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