MBM29LV800BE90 데이터 시트보기 (PDF) - Fujitsu

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MBM29LV800BE90

FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT

Fujitsu 

MBM29LV800TE/BE60/70/90

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The standard MBM29LV800TE/BE offer access times 60 ns, 70 ns and 90 ns, allowing operation of high-speed

microprocessors without wait state. To eliminate bus contention, the devices have separate chip enable (CE) ,

write enable (WE) , and output enable (OE) controls.

The MBM29LV800TE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV800TE/BE are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV800TE/BE are erased when shipped from the

factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low VCC detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally resets to the read mode.

The MBM29LV800TE/BE also have hardware RESET pins. When this pin is driven low, execution of any

Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then

reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset

occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically

reset to the read mode and will have erroneous data stored in the address locations being programmed or

erased. These locations need re-writing after the Reset. Resetting the device enables the system’s

microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29LV800TE/BE memory electrically erase all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

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