MC100EL05(2016) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100EL05 Datasheet PDF : 8 Pages
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MC10EL05, MC100EL05
5 V ECL 2‐Input Differential
AND/NAND
Description
The MC10EL/100EL05 is a 2-input differential AND/NAND gate.
The device is functionally equivalent to the E404 device with higher
performance capabilities. With propagation delays and output transition
times significantly faster than the E404, the EL05 is ideally suited for
those applications which require the ultimate in AC performance.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the EL05
to also be used as a 2-input differential OR/NOR gate.
The differential inputs employ clamp circuitry so that under open input
conditions (pulled down to VEE) the input to the AND gate will be
HIGH. In this way, if one set of inputs is open, the gate will remain active
to the other input.
The 100 Series contains temperature compensation.
Features
• 275 ps Propagation Delay
• ESD Protection:
♦ > 1 kV Human Body Model,
♦ > 100 V Machine Model
• PECL Mode Operating Range:
♦ VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range:
♦ VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity
♦ Level 1 for SOIC−8
♦ Level 3 for TSSOP−8
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating:
♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 44 devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751−07
8
1
TSSOP−8
DT SUFFIX
CASE 948R−02
MARKING DIAGRAMS*
8
HEL05
ALYW
G
1
8
HL05
ALYWG
G
1
8
KEL05
ALYW
G
1
8
KL05
ALYWG
G
1
H = MC10
L = Wafer Lot
K = MC100
Y = Year
4O = MC10
W = Work Week
2C = MC100
D = Date Code
A = Assembly Location G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
D0 1
D0 2
8 VCC
7Q
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
D1 3
6Q
D1 4
5 VEE
Figure 1. Logic Diagram and Pinout
Assignment
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 7
Publication Order Number:
MC10EL05/D
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