MC100ELT23DR2(2001) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100ELT23DR2 Datasheet PDF : 8 Pages
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MC100ELT23
5VĄDual Differential PECL
to TTL Translator
The MC100ELT23 is a dual differential PECL to TTL translator.
Because PECL (Positive ECL) levels are used, only +5 V and ground are
required. The small outline 8-lead package and the dual gate design of the
ELT23 makes it ideal for applications which require the translation of a
clock and a data signal.
The PECL inputs are differential; therefore, the MC100ELT23 can
accept any standard differential PECL input referenced from a VCC of 5.0
V.
• 3.5 ns Typical Propagation Delay
• 24 mA TTL Outputs
• Flow Through Pinouts
• ESD Protection: >2 KV HBM, > 400 V MM
• The 100 Series Contains Temperature Compensation
• Operating Range VCC= 4.75 V to 5.25 V with GND= 0 V
• Internal Input Pulldown Resistors
• Q Output Will Default High with Inputs Left Open or < 1.3 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 91 devices
D0 1
8 VCC
D0 2
PECL
D1 3
7 Q0
TTL
6 Q1
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
KLT23
ALYW
1
8
1
TSSOP–8
DT SUFFIX
CASE 948R
8
KT23
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100ELT23D
SO–8
98 Units / Rail
MC100ELT23DR2
SO–8
2500 / Reel
MC100ELT23DT
TSSOP–8 98 Units / Rail
MC100ELT23DTR2 TSSOP–8 2500 / Reel
D1 4
5 GND
Figure 1. 8–Lead Pinout and Logic Diagram
(Top View)
PIN DESCRIPTION
PIN
FUNCTION
Qn
Dn, Dn
VCC
GND
TTL Outputs
PECL Differential Inputs
Positive Supply
Ground
© Semiconductor Components Industries, LLC, 2001
1
June, 2001 – Rev. 5
Publication Order Number:
MC100ELT23/D
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