MC100EPT21DTG(2012) 데이터 시트보기 (PDF) - ON Semiconductor

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MC100EPT21DTG
(Rev.:2012)

3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

ON Semiconductor 

MC100EPT21

NC 1

D2

8 VCC

LVTTL

7Q

D3

LVPECL

6 NC

VBB 4

5 GND

Figure 1. Logic Diagram and 8−Lead Pinout (Top View)

Table 1. PIN DESCRIPTION

PIN

FUNCTION

Q

D*, D*

VCC

VBB

GND

NC

LVTTL/LVCMOS Output

Differential LVPECL/LVDS/CML Input

Positive Supply

Output Reference Voltage

Ground

No Connect

EP

(DFN8 only) Thermal exposed pad must be

connected to a sufficient thermal conduit. Elec-

trically connect to the most negative supply

(GND) or leave unconnected, floating open.

* Pin will default to 1/2 of VCC when left open.

Table 2. ATTRIBUTES

Characteristics

Internal Input Pulldown Resistor

D

Internal Input Pulldown Resistor

D

Internal Input Pullup Resistor

D, D

ESD Protection

Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

SOIC−8

TSSOP−8

DFN8

Flammability Rating

Oxygen Index: 28 to 34

Transistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Value

50 kW

50 kW

50 kW

> 1.5 kV

> 100 V

> 2 kV

Level 1

Level 3

Level 1

UL 94 V−0 @ 0.125 in

81 Devices

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