MC100LVEL33(2016) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100LVEL33 Datasheet PDF : 7 Pages
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MC100LVEL33
Reset 1
CLK 2
CLK 3
8 VCC
R
7Q
÷4
6Q
VBB 4
5 VEE
Figure 1. Logic Diagram and Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK*, CLK**
Q, Q
Reset*
VBB
VCC
VEE
ECL Differential Clock Inputs
ECL Differential Data ÷4 Outputs
ECL Asynch Reset
Reference Voltage Output
Positive Supply
Negative Supply
* Pins will default LOW when open due to internal 75 kW
resistor to VEE
** Pins will default to 1/2 VCC when open due to internal
resistors: 75 kW to VEE and 75 kW to VCC
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI ≤ VCC
VI ≥ VEE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
50
mA
100
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
± 0.5
−40 to +85
−65 to +150
190
130
mA
°C
°C
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
TSSOP−8
TSSOP−8
41 to 44 ±5%
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
TSSOP−8
41 to 44 ±5%
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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