MC100LVEL34(2014) 데이터 시트보기 (PDF) - ON Semiconductor

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MC100LVEL34
(Rev.:2014)

3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip

ON Semiconductor 

MC100LVEL34

Q0 1

Q0 2

VCC 3

Q1 4

Q1 5

VCC 6

Q

÷2

R

Q

÷4

R

16 VCC

QD

R

15 EN

14 NC

13 CLK

12 CLK

11 VBB

Q2 7

Q2 8

Q

÷8

R

10 MR

9 VEE

Warning: All VCC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Figure 1. 16−Lead Pinout (Top View) and Logic Diagram

Table 1. PIN DESCRIPTION

PIN

FUNCTION

CLK*, CLK**

ECL Diff Clock Inputs

EN*

ECL Sync Enable

MR*

ECL Master Reset

Q0, Q0

ECL Diff ÷2 Outputs

Q1, Q1

ECL Diff ÷4 Outputs

Q2, Q2

ECL Diff ÷8 Outputs

VBB

Reference Voltage Output

VCC

Positive Supply

VEE

Negative Supply

NC

No Connect

* Pins will default LOW when left open.

***Pins will default to VCC/2 when left open.

Table 2. FUNCTION TABLE

CLK

EN

MR

FUNCTION

Z

L

L

ZZ

H

L

X

X

H

Z = Low-to-High Transition

ZZ = High-to-Low Transition

Divide

Hold Q0−3

Reset Q0−3

Table 3. ATTRIBUTES

Characteristics

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

SOIC−16

TSSOP−16

Flammability Rating

Oxygen Index: 28 to 34

Transistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Value

75 kW

37.5 kW

> 2 kV

> 200 V

> 2 kV

Pb Pkg

Pb−Free Pkg

Level 1

Level 1

Level 1

Level 1

UL 94 V−0 @ 0.125 in

210 Devices

http://onsemi.com

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