MC100LVEL34(2014) 데이터 시트보기 (PDF) - ON Semiconductor

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MC100LVEL34
(Rev.:2014)

3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip

ON Semiconductor 

MC100LVEL34

There are two distinct functional relationships between the Master Reset and Clock:

Internal Clock

Disabled

MR

Internal Clock

Enabled

CLK

Q0

Q1

Q2

EN

CASE 1: If the MR is deasserted (H−L), while the Clock is still high, the

outputs will follow the second ensuing clock rising edge.

Internal Clock

Disabled

Internal Clock

Enabled

MR

CLK

Q0

Q1

Q2

EN

CASE 2: If the MR is deasserted (H−L), after the Clock has transitioned low, the

outputs will follow the third ensuing clock rising edge.

Figure 2. Timing Diagrams

The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal

divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge

of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-

tionships.

TRR

CLOCK

TRR

CLOCK

MR

OUTPUT

CASE 1

MR

OUTPUT

Figure 3. Reset Recovery Time

CASE 2

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