MC100LVEP34 데이터 시트보기 (PDF) - ON Semiconductor
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MC100LVEP34 Datasheet PDF : 12 Pages
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MC100LVEP34
Q0 1
Q0 2
VCC 3
Q1 4
Q1 5
VCC 6
Q
÷2
R
Q
÷4
R
16 VCC
QD
R
15 EN
14 NC
13 CLK
12 CLK
11 VBB
Q2 7
Q2 8
Q
÷8
R
10 MR
9 VEE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 16−Lead Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Function
CLK*, CLK**
ECL Diff Clock Inputs
EN*
ECL Sync Enable
MR*
ECL Master Reset
Q0, Q0
ECL Diff ÷2 Outputs
Q1, Q1
ECL Diff ÷4 Outputs
Q2, Q2
ECL Diff ÷8 Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
* Pins will default LOW when left open.
**Pins will default to VCC/2 when left open.
Table 2. FUNCTION TABLE
CLK
EN
MR
Z
L
L
ZZ
H
L
X
X
H
Z = Low−to−High Transition
ZZ = High−to−Low Transition
FUNCTION
Divide
Hold Q0−3
Reset Q0−3
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