MC100E196 데이터 시트보기 (PDF) - ON Semiconductor
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MC100E196 Datasheet PDF : 12 Pages
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MC10E196, MC100E196
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D2 D3 D4 D5 D6 D7 NC
25 24 23 22 21 20 19
D1 26
18 FTUNE
D0 27
17 NC
LEN 28
16 VCC
VEE 1
IN 2
MC10E196
MC100E196
15 VCCO
14 Q
IN 3
13 Q
VBB 4
12 VCCO
5 6 7 8 9 10 11
NC NC EN
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28
(Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
VBB
VCC, VCCO
VEE
NC
ECL Signal Input
ECL Input Enable (H Forces Q Low)
ECL MUX Select Inputs
ECL Signal Output
ECL Latch Enable
ECL Min Delay Set
ECL Max Delay Set
ECL Cascade Signal
ECL Linear Voltage Input
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. TRUTH TABLE
EN
L
EN
H
LEN
L
LEN
H
SETMIN L
SETMIN H
SETMAX L
SETMAX H
Q = IN
Q Logic Low
Pass Through D[0:10]
Latch D[0:10]
Normal Mode
Min Delay Path
Normal Mode
Max Delay Path
VBB
11 0
0
IN
IN
1
1
EN * 1.25
* 1.5
VEE
LEN
SET MIN
SET MAX
0
11
0
1 11
0
4 GATES
1
7 BIT LATCH
0
8 GATES
1
16 GATES
LEN
Q
LATCH
D
FTUNE
0
1
0
Q
Q
11
LINEAR
CASCADE
RAMP
CASCADE
CASCADE
D0
D1
* delays are 25% or 50% longer than
* standard (standard ≈ 80 ps)
D2
D3
D4
D5
D6
D7
Figure 2. Logic Diagram − Simplified
http://onsemi.com
2
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