MC100E196 데이터 시트보기 (PDF) - ON Semiconductor

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MC100E196

5VECL Programmable Delay Chip

ON Semiconductor 

MC10E196, MC100E196

When the SET MAX pin of chip #1 is asserted the D0 and

D1 latches will be reset while the rest of the latches will be

set. In addition, to maintain monotonicity an additional gate

delay is selected in the cascade circuitry. As a result when D7

of chip #1 is asserted the delay increases from 31.75 gates

to 32 gates. A 32 gate delay is the maximum delay setting for

the E196.

When cascading multiple PDC’s it will prove more cost

effective to use a single E196 for the Most Significant Bit

(MSB) of the chain while using E195 for the lower order

bits. This is due to the fact that only one fine tune input is

needed to further reduce the delay step resolution.

A7

INPUT

ADDRESS BUS (A0−A6)

LINEAR

INPUT

D1

FTUNE

D0

E196

LEN

Chip #1

VCC

VEE

VCC0

IN

Q

IN

Q

VBB

VCC0

D1

FTUNE

D0

E196

LEN

Chip #2

VEE

IN

IN

VBB

VCC

VCC0

Q

Q

VCC0

OUTPUT

Figure 3. Cascading Interconnect Architecture

TO SELECT MULTIPLEXERS

BIT 0

D0 Q0

LEN

Reset Reset

SET MIN

SET MAX

BIT 1

D1 Q1

LEN

Reset Reset

BIT 2

D2 Q2

LEN

Reset Reset

BIT 3

D3 Q3

LEN

Reset Reset

BIT 4

D4 Q4

LEN

Reset Reset

BIT 5

D5 Q5

LEN

Reset Reset

BIT 6

D6 Q6

LEN

Reset Reset

Figure 4. Expansion of the Latch Section of the E196 Block Diagram

BIT 7

D7 Q7

LEN

Reset Reset

CASCADE

CASCADE

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