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MC100ELT21D Datasheet PDF : 8 Pages
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MC10ELT21, MC100ELT21
5 V Differential PECL to
TTL Translator
Description
The MC10ELT/100ELT21 is a differential PECL to TTL translator.
Because PECL (Positive ECL) levels are used, only +5 V and ground
are required. The small outline 8-lead package and the single gate of
the ELT21 makes it ideal for those applications where space,
performance and low power are at a premium.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
• 3.5 ns Typical Propagation Delay
• 24 mA TTL Output
• Flow Through Pinouts
• Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V
• Q Output Will Default LOW with Inputs Left Open or < 1.3 V
• Pb−Free Packages are Available
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
8
HLT21
ALYW
G
1
8
KLT21
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HT21
ALYWG
G
1
8
KT21
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
14
H = MC10
A = Assembly Location
K = MC100
L = Wafer Lot
5C = MC10
Y = Year
2Q = MC100
W = Work Week
M = Date Code G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 11
Publication Order Number:
MC10ELT21/D
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