MC10H160 데이터 시트보기 (PDF) - ON Semiconductor
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MC10H160 Datasheet PDF : 6 Pages
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MC10H160
12−Bit Parity
Generator−Checker
Description
The MC10H160 is a 12−bit parity generator−checker. The output
goes high when an odd number of inputs are high providing the odd
parity function. Unconnected inputs are pulled to a logic low allowing
parity detection and generation for less than 12−bits. The MC10H160
is a functional pin duplication of the standard 10K family part with
100% improvement in propagation delay and no increase in
power−supply current.
Features
• Propagation Delay, 2.5 ns Typical
• Power Dissipation, 320 mW Typical
• Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
• Voltage Compensated
• MECL 10K™ Compatible
• Pb−Free Packages are Available*
LOGIC DIAGRAM
3
4
VCC1 = PIN 1
5
VCC2 = PIN 16
TRUTH TABLE
6
VEE = PIN 8
INPUT OUTPUT
7
Sum of
9
10
2
High Level
Inputs
Pin 2
11
Even
Low
12
Odd
High
13
14
15
DIP
PIN ASSIGNMENT
VCC1
1
OUT
2
IN1
3
IN2
4
IN3
5
IN4
6
IN5
7
VEE
8
16
VCC2
15
IN12
14
IN11
13
IN10
12
IN9
11
IN8
10
IN7
9
IN6
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 8
http://onsemi.com
MARKING DIAGRAMS*
CDIP−16
L SUFFIX
CASE 620A
16
MC10H160L
AWLYYWW
1
16
16
1
PDIP−16
P SUFFIX
CASE 648
MC10H160P
AWLYYWWG
1
10H160
ALYWG
SOEIAJ−16
CASE 966
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
10H160G
AWLYYWW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC10H160/D
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