MC145506 데이터 시트보기 (PDF) - Motorola => Freescale
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MC145506 Datasheet PDF : 24 Pages
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Logic
Level
Freescale Semiconductor, Inc.
Table 2. Summary of Operation Conditions User Programmed Through Pins VDD, VAG, and VSS
Pin
Programmed
Mu/A
RSI
Peak
Overload
Voltage
VLS
VDD
Mu–Law Companding Curve and D3/D4 Digital
Formats with Zero Code Suppress
3.78 CMOS
Logic Levels
VAG
VSS
Mu–Law Companding Curve and Sign Magnitude
Data Format
A–Law Companding Curve and CCITT Digital
Format
2.50
TTL Input Levels, VAG Up;
HCMOS Output Levels, VAG to VDD
3.15
TTL Levels, VSS Up;
HCMOS Output Levels, VSS to VDD
TDE
tsu2
tP4
tsu1
fCL
tw
tw
TDC
1
2
3
4
5
6
7
tP1
tP3
tP3
TDD
*
MSB
* Data output during this time will vary depending on TDC rate and TDE timing.
tsu8
8
9
10
tP2
LSB
11
tP2
PCM WORD REPEATED
Figure 2. Transmit Timing Diagram
tw
RCE
tsu4
tsu3
RDC
1
2
tsu5
RDD DON’T
CARE
th
MSB
fCL
tw
tw
3
4
5
6
7
8
9
LSB
Figure 3. Receive Timing Diagram
10
11
DON’T
CARE
tw
MSI
tsu7
tsu6
tw
tw
CCI
1
2
3
4
5
6
7
8
9
10
11
Figure 4. MSI/CCI Timing Diagram
MOTOROLA
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