MC14553BDW 데이터 시트보기 (PDF) - Motorola => Freescale
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MC14553BDW Datasheet PDF : 8 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCCHÎÎÎÎhAarRaÎÎÎÎcAteCrÎÎÎÎTisEtiRcÎÎÎÎISTÎÎÎÎICSÎÎÎÎ(CLÎÎÎÎ= 50ÎÎÎÎpFFiÎÎÎÎ,gTuAreÎÎÎÎ= 25ÎÎÎÎ_C)ÎÎÎÎSymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time
2a
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Clock to BCD Out
2a
tTLH,
tTHL
5.0
10
15
tPLH,
5.0
tPHL
10
15
ns
—
100
200
—
50
100
—
40
80
—
900
1800
ns
—
500
1000
—
200
400
Clock to Overflow
2a
tPHL
5.0
—
600
1200
ns
10
—
400
800
15
—
200
400
Reset to BCD Out
2b
tPHL
5.0
—
900
1800
ns
10
—
500
1000
15
—
300
600
Clock to Latch Enable Setup Time
2b
Master Reset to Latch Enable Setup Time
tsu
5.0
600
300
—
ns
10
400
200
—
15
200
100
—
Removal Time
Latch Enable to Clock
2b
trem
5.0
– 80
– 200
—
ns
10
– 10
– 70
—
15
0
– 50
—
Clock Pulse Width
2a
tWH(cl)
5.0
550
275
—
ns
10
200
100
—
15
150
75
—
Reset Pulse Width
2b
tWH(R)
5.0
1200
600
—
ns
10
600
300
—
15
450
225
—
Reset Removal Time
—
trem
5.0
– 80
– 180
—
ns
10
0
– 50
—
15
20
– 30
—
Input Clock Frequency
2a
fcl
5.0
—
1.5
0.9
MHz
10
—
5.0
2.5
15
—
7.0
3.5
Input Clock Rise Time
2b
tTLH
5.0
10
15
No
ns
Limit
Disable, MR, Latch Enable
Rise and Fall Times
—
tTLH,
5.0
—
—
15
µs
tTHL
10
—
—
5.0
15
—
—
4.0
Scan Oscillator Frequency
(C1 measured in µF)
1
fosc
5.0
—
1.5/C1
—
Hz
10
—
4.2/C1
—
15
—
7.0/C1
—
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14553B
3
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