MC14526B 데이터 시트보기 (PDF) - ON Semiconductor
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MC14526B Datasheet PDF : 10 Pages
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MC14526B
FUNCTION TABLE
Inputs
Output
Preset Cascade
Clock Reset Inhibit Enable Feedback “0”
Resulting
Function
X
H
X
L
L
L Asynchronous reset*
X
H
X
H
L
H Asynchronous reset
X
H
X
X
H
H Asynchronous reset
X
L
X
H
X
L Asynchronous preset
L
H
L
X
L Decrement inhibited
L
L
L
X
L Decrement inhibited
L
L
L
L
L No change** (inactive edge)
H
L
L
L
L No change** (inactive edge)
L
L
L
L
L Decrement**
H
L
L
L
L Decrement**
X = Don’t Care
NOTES:
** Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
Q3 1
P3 2
PE 3
INHIBIT 4
P0 5
CLOCK 6
7
VSS 8
16 VDD
15 Q2
14 P2
13 CF
12 0"
11 P1
10 RESET
9 Q1
Figure 1. Pin Assignment
PIN DESCRIPTIONS
Preset Enable (Pin 3) — If Reset is low, a high level on the other than all zeroes, the “0” output is valid after the rising
Preset Enable input asynchronously loads the counter with edge of Preset Enable (when Cascade Feedback is high). See
the programmed values on P0, P1, P2, and P3.
the Function Table.
Inhibit (Pin 4) — A high level on the Inhibit input pre−
Cascade Feedback (Pin 13) — If the Cascade Feedback
vents the Clock from decrementing the counter. With Clock input is high, a high level is generated at the “0” output when
(pin 6) held high, Inhibit may be used as a negative edge clock the count is all zeroes. If Cascade Feedback is low, the “0”
input.
output depends on the Preset Enable input level. See the
Clock (Pin 6) — The counter decrements by one for each Function Table.
rising edge of Clock. See the Function Table for level
P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
requirements on the other inputs.
data inputs. P0 is the LSB.
Reset (Pin 10) — A high level on Reset asynchronously
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is synchronous counter outputs. Q0 is the LSB.
high, causes the “0” output to go high.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one
VSS (Pin 8) — The most negative power supply potential.
This pin is usually ground.
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
VDD (Pin 16) — The most positive power supply potential.
VDD may range from 3.0 to 18 V with respect to VSS.
STATE DIAGRAM
MC14526B
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
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