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MC33999 Datasheet PDF : 16 Pages
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Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V ≤ SOPWR ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
RL = 56 Ω (Note 16)
Output Turn ON Delay Time (Note 17)
SR
V/µs
1.0
2.0
10
t DLY(on)
1.0
15
50
µs
Output Turn OFF Delay Time (Note 17)
t DLY(off)
1.0
15
50
µs
Output ON Short Fault Disable Report Delay (Note 18)
t DLY(short)
100
–
450
µs
Output OFF Open Fault Delay Time (Note 18)
t DLY(open)
100
–
450
µs
Output PWM Frequency
t FREQ
–
–
2.0
kHz
DIGITAL INTERFACE TIMING
Required Low State Duration on VPWR for Reset
VPWR ≤ 0.2 V (Note 19)
t RST
µs
–
–
10
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t LEAD
100
–
–
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
t LAG
50
–
–
ns
SI to Falling Edge of SCLK (Required Setup Time)
t SI(su)
16
–
–
ns
Falling Edge of SCLK to SI (Required Setup Time)
t SI (hold)
20
–
–
ns
SI, CS, SCLK Signal Rise Time (Note 20)
t r (SI)
–
5.0
–
ns
SI, CS, SCLK Signal Fall Time (Note 20)
t f (SI)
–
5.0
–
ns
Time from Falling Edge of CS to SO Low Impedance (Note 21)
t SO (en)
–
–
50
ns
Time from Rising Edge of CS to SO High Impedance (Note 22)
tSO (dis)
–
–
50
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 23)
t VALID
–
25
80
ns
Notes
16. Output slew rate measured across a 56 Ω resistive load.
17. Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.
18. Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.
19. This parameter is guaranteed by design but is not production tested.
20. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
21. Time required for valid output status data to be available on SO pin.
22. Time required for output status data to be terminated at SO pin.
23. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDoErVeICEInDfAoTrAmation On This Product,
Go to: www.freescale.com
33999
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