Freescale Semiconductor, Inc.
Table 2 MCU Pin Characteristics (Continued)
Pin
Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
PCS0/SS
Bo
Yes2
Yes
I/O
PQS3
PCS[3:1]
Bo
Yes2
Yes
I/O
PQS[6:4]
RESET
Bo
Yes
Yes
—
—
RMC
A
Yes
Yes
I/O
PE3
R/W
A
Yes
No
—
—
RXD
—
No
Yes
—
—
SCK
Bo
Yes2
Yes
I/O
PQS2
SIZ[1:0]
B
Yes
No
I/O
PE[7:6]
TSC
—
Yes
Yes
—
—
TXD
Bo
Yes2
Yes
I/O
PQS7
XFC
—
—
—
—
—
XRTC
—
—
—
—
—
XTAL
—
—
—
—
—
NOTES:
1. HALT and BERR synchronized only if late HALT or BERR.
2. DATA[15:0] synchronized during reset only. MODCLK and QSM pins synchronized only if used as port I/O pins.
2.2 MCU Power Connections
Table 3 MCU Power Connections
VDDSYN
VDDE, VSSE
VDDI, VSSI
VRTC
VSSRTCOSC
Clock Synthesizer
External periphery power (source and drain)
Internal module power (source and drain)
RTCSM/RAMSM standby power
Ground connection for real-time clock oscillator
2.3 MCU Driver Types
Table 4 MCU Output Driver Types
Type
A
Ao
Aw
B
Bw
Bo
Description
Output-only signals that are always driven; no external pull-up required
Type A output that can be operated in an open drain mode
Type A output with weak P-channel pull-up during reset
Three-state output that includes circuitry to pull up output before high impedance
is established, to ensure rapid rise time. An external holding resistor is required to
maintain logic level while the pin is in the high-impedance state.
Type B output with weak P-channel pull-up during reset
Type B output that can be operated in an open-drain mode
MOTOROLA
8
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MC68CK338
MC68CK338TS/D