SY100E151JCTR(1998) 데이터 시트보기 (PDF) - Micrel
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SY100E151JCTR Datasheet PDF : 4 Pages
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6-BIT D
REGISTER
SY10E151
SY100E151
FEATURES
s 1100MHz toggle frequency
s Extended 100E VEE range of –4.2V to –5.46V
s Differential outputs
s Asynchronous Master Reset
s Dual clocks
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75KΩ input pulldown resistors
s Fully compatible with Motorola MC10E/100E151
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK1, CLK2) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK1 or CLK2 (or both). When
both CLK1 and CLK2 are at a logic LOW, data enters the
master and is transferred to the slave when either CLK1 or
CLK2 (or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
CLK1
CLK2
M
R
D
Q0
R
Q0
D
Q1
R
Q1
D
Q2
R
Q2
D
Q3
R
Q3
D
Q4
R
Q4
D
Q5
R
Q5
PIN CONFIGURATION
D5
D4
D3
VEE
D2
D1
D0
25 24 23 22 21 20 19
26
18
27
17
28
16
PLCC
1
TOP VIEW
15
2
J28-1
14
3
13
4
12
5 6 7 8 9 10 11
Q4
Q4
VCC
Q3
Q3
Q2
Q2
PIN NAMES
Pin
D0–D5
CLK1, CLK2
MR
Q0–Q5
Q0–Q5
VCCO
1
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverting Outputs
VCC to Output
Rev.: D
Amendment: /0
Issue Date: November, 1998
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