SPT7610 데이터 시트보기 (PDF) - Fairchild Semiconductor
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SPT7610 Datasheet PDF : 10 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Negative Supply Voltage (AVEE TO GND) . –7.0 to +0.5 V
Ground Voltage Differential ........................ –0.5 to +0.5 V
Input Voltage
Analog Input Voltage ................................ +0.5 V to AVEE
Reference Input Voltage ........................... +0.5 V to AVEE
Digital Input Voltage .................................. +0.5 V to AVEE
Reference Current VRT to VRB ............................ +20 mA
Output
Digital Output Current ................................... 0 to –25 mA
Temperature
Operating Temperature, Ambient ............... –40 to +85 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature ............................... –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, AVEE = –5.2 V, VRB = –1.00 V, VRM = –0.5 V, VRT = 0.00 V, ƒCLK = 1000 MSPS, Duty Cycle = 50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
SPT7610
MIN
TYP
MAX UNITS
Resolution
6
Bits
DC Accuracy
Integral Linearity
Differential Linearity
No missing codes
VI
–0.5
+0.5 LSB
VI
–0.5
+0.5 LSB
VI
Guaranteed
Analog Input
Offset Error VRT
VI
Offset Error VRB
VI
Input Voltage Range
VI
Input Capacitance
Over Full Input Range
V
Input Resistance
V
Input Bias Current
VI
Bandwidth
Small Signal
V
Input Slew Rate
V
Clock Synchronous Input Currents
V
–30
+30 mV
–30
+30 mV
–1
0.0
Volts
8
pF
50
kΩ
200
400 µA
1.4
GHz
5
V/ns
2
µA
Power Supply Requirements
Supply Current
Power Dissipation
VI
550
770 mA
VI
2.85
4.0
W
Reference Inputs
Ladder Resistance
Reference Bandwidth
VI
60
80
120 Ω
V
100
MHz
Digital Outputs
Digital Output High Voltage
Digital Output Low Voltage
Digital Inputs
Digital Input High Voltage
(CLK, NCLK)
Digital Input Low Voltage
(CLK, NCLK)
Clock Input Swing
(CLK, NCLK)
Maximum Sample Rate
Clock Low Width, TPW0
Clock High Width, TPW1
R1 = 50 Ω to –2 V
R1 = 50 Ω to –2 V
VI
–1.2
–0.9
Volts
VI
–1.8
–1.5 Volts
VI
–1.1
–0.7 Volts
VI
–2.0
–1.5 Volts
IV
100
700
VI
1000
1200
VI
0.5
0.4
VI
0.5
0.4
mV
MSPS
ns
ns
SPT7610
2
1/21/02
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