MC88916 데이터 시트보기 (PDF) - Motorola => Freescale

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MC88916

Low Skew CMOS PLL Clock Driver With Processor Reset

Motorola => Freescale 

MC88916

88916

2X_Q

OUTPUT

Zo (CLOCK

Rs

TRACE)

Rs = Zo – 7Ω

68040

PCLK

CLOCK

RP INPUT

RP = 1.5Zo

Figure 3. MC68040 PCLK Input Termination Scheme

INTERNAL

LOGIC

RST_OUT PIN

VCC

1K

CL

ANALOG GND

Figure 4. RST_OUT Test Circuit

16.5MHz

CRYSTAL

OSCILLATOR

SYNC

MR

PLL_EN

RST_IN

2X_Q

Q0

Q1

Q2

Q3

66MHz PCLK OUTPUT

33MHz

B–CLOCK

AND SYSTEM

OUTPUTS

Q/2

RST_OUT

Figure 5. Logical Representation of the MC88916 With

Input/Output Frequency Relationships

SYNC Input

tSKEWall

tSKEWf

tCYCLE SYNC Input

tSKEWr

tSKEWf

tSKEWr

Q0–Q2 Outputs

Q3 Output

tCYCLE ‘Q’ Outputs

2X_Q Output

Q/2 Output

Figure 6. Output/Input Switching Waveforms and Timing Relationships

Timing Notes

1. The MC88916 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%

duty cycle.

2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as

‘windows’, not as a ± deviation around a center point.

TIMING SOLUTIONS

7

BR1333 — REV 5

MOTOROLA

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