MC9S12B128 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC9S12B128

16-Bit Microcontroller

Freescale Semiconductor 

Features

2 Features

NOTE

Not all features listed here are available in all configurations.

Additional information about D and B family inter-operability is given in:

EB386 “HCS12 D-Family Compatibility Considerations” and

EB388 “Using the HCS12 D_Family as a development platform for the

HCS12 B family”

• 16-bit CPU12

— Upward compatible with M68HC11 instruction set

— Interrupt stacking and programmer’s model identical to M68HC11

— 20-bit ALU

— Instruction queue

— Enhanced indexed addressing

• Multiplexed bus

— Single chip or expanded

— 16 address/16 data wide or 16 address/8 data narrow modes

— External address space 1MByte for Data and Program space (112 pin package only)

• Wake-up interrupt inputs depending on the package option

— 8-bit port H

— 4-bit port J

— 8-bit port P shared with PWM

• Memory options

— 64K, 128K, 256K Byte Flash EEPROM

— 1K, 2K Byte EEPROM

— 2K, 4K and 8K Byte RAM

• Analog-to-Digital Converter

— 16-channels for 112 Pin Package, 8 channels for 80 Pin package options, 10-bit resolution

— External conversion trigger capability

• 1M bit per second, CAN 2.0 A, B software compatible module

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error and wake-up

— Low-pass filter wake-up function

— Loop-back for self test operation

• Input Capture/Output Compare Timer (TIM)

MC9S12B Family, Rev. 2.8

2

Freescale Semiconductor

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