3S12XDT256 데이터 시트보기 (PDF) - Freescale Semiconductor

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3S12XDT256

16-bit Microprocessor Family

Freescale Semiconductor 

Features

• Up to two IIC modules (see Table 2)

• Compatible with I2C Bus standard

• Multi-master operation

• Software programmable for one of 256 different serial clock

frequencies

• Software selectable acknowledge bit

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from master

to slave

• Calling address identification interrupt

• Start and stop signal generation/detection

• Repeated start signal generation

• Acknowledge bit generation/detection

• Bus busy detection

• supports 400 Kbps

• Background debug controller (BDM) with single-wire interface

– Non-intrusive memory access commands

– Supports in-circuit programming of on-chip non-volatile memory

– Supports security

• Four comparators A, B, C and D

– Each can monitor CPU or XGATE busses

– A and C compares 23-bit address bus and 16-bit data bus with

mask register

– B and D compares 23-bit address bus only

– Three modes: simple address/data match, inside address range

or outside address range

• 64 x 64-bit circular trace buffer to capture change-of-flow addresses

or address and data of every access

• Tag-type or force-type hardware breakpoint requests

• Power-on reset (POR)

• illegal address detection with reset

• Low-voltage detection with interrupt or reset

• up to 117 general-purpose input/output (I/O) pins depending on the

package option and 2 input-only pins

• Hysteresis and configurable pullup/pulldown device on all input pins

• Configurable drive strength on all output pins

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

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