MH8S64DALD 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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MH8S64DALD Datasheet PDF : 55 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
PIN FUNCTION
CK
(CK0 ~ CK3)
CKE0
/S
(/S0,2)
/RAS,/CAS,/WE
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11
BA0,1
DQ0-63
DQMB0-7
Vdd,Vs s
Input
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL
Input Serial clock for serial PD
SDA
SA0-3
Output Serial data for serial PD
Input Address input for serial PD
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 6 / 55 )
17.Sep.1999
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