ML7021 데이터 시트보기 (PDF) - Oki Electric Industry

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ML7021

Single Rail CODEC

Oki Electric Industry 

¡ Semiconductor

ML7021

PIN DESCRIPTIONS (1/4)

Pin

Symbol Type

Description

1

NLP

I Control pin for the center clipping function.

This pin forces the SOUT output to a minimum value when the SOUT

signal is below –54 dBm0. Effective for reducing low-level noise.

• Single Chip or Master Chip in a Cascade Connection

"H": Center clip ON

"L": Center clip OFF

• Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of the

INT signal or the rising edge of the RST signal.

2

HCL

I Through mode control.

When this pin is in the through mode,

RIN and SIN data is output to ROUT and SOUT. At the same time, the

coefficient of the adaptive FIR filter is cleared.

• Single Chip or Master Chip in a Cascade Connection

"H": Through mode

"L": Normal mode (echo canceler operates)

• Slave Chip in a Cascade Connection

Same as the master chip

This input signal is loaded in synchronization with the falling edge of the

INT signal or the rising edge of the RST signal.

3

ADP

I AFF coefficient control.

This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets

the coefficient to a fixed value, when this pin is configured to be the

coefficient fix mode.

This pin is used when holding the AFF coefficient which has been once

converged.

• Single Chip or Master Chip in a Cascade Connection

"H": Coefficient fix mode

"L": Normal mode (coefficient update)

• Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of the

INT signal or the rising edge of the RST signal.

4

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