ML7021 데이터 시트보기 (PDF) - Oki Electric Industry
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ML7021 Datasheet PDF : 24 Pages
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¡ Semiconductor
ML7021
(4/4)
Pin
Symbol Type
Description
22
SYNCO
O 8 kHz sync signal for the PCM CODEC.
Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin.
Leave it open if using an external SYNC.
23
SCKO
O Transmit clock signal (256 kHz) for the PCM CODEC.
Connect to the SCK pin and the PCM CODEC transmit/receive clock pin.
Leave it open if using an external SCK.
24
RST
I Reset signal.
"L": Reset mode
"H": Normal operation mode
Due to initialization, input signals are disabled for 100 ms after reset
(after RST is returned from L to H).
Input the basic clock during the reset.
Output pins during the reset are in the following states :
High impedance: SOUT, ROUT
"L": WDT
"H": OF1, OF2
Not affected: X2, SYNCO, SCKO, IRLD, MCKO
After the power is turned on, initialize the LSI's internal registers by your
execution of HÆL sequence 1ms later than the master clock starts
normal oscilation.
This LSI starts a normal operation by releasing this pin to H after the
HÆL sequence above.
Here, this pin must stay L for 1ms or longer.
25
WDT
O Test program end signal.
This signal is output when one cycle (8kHz) of processing is completed.
Leave it open.
26
GC
I Input signal by which the gain controller for the RIN input is
controlled and the RIN input level is controlled and howling is prevented.
The gain controller adjusts the RIN input level when it is –10 dBm0 or
above. RIN input levels from –10 to –1.5 dBm0 will be suppressed to
–10 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –1.5 dBm0 will always be attenuated by 8.5 dB.
• Single Chip or Master Chip in a Cascade Connection
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.
• Slave Chip in a Cascade Connection
Fixed at "L"
This pin is loaded in synchronization with the falling edge of the INT signal
or the rising edge of RST.
28
MCKO
O Basic clock (19.2 MHz).
7
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