ML7048 데이터 시트보기 (PDF) - Oki Electric Industry

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ML7048

3-Channel Single Rail CODEC

Oki Electric Industry 

1Semiconductor

PEDL7048-01-01

ML7048-01

PIN FUNCTIONAL DESCRIPTION

AIN1+, AIN2+, AIN3+, AIN1–, AIN2–, AIN3–, QSX1, GSX2, GSX3

AIN1+, AIN1– and GSX1 are the transmit inputs and transmit level adjustment pins for Channel 1, AIN2+, AIN2–

and GSX2 are those for Channel 2. AIN3+, and AIN3– and GSX3 are those for Channel 3.

AIN1+, AIN2+ and AIN3+ are non-inverting inputs for the op-amp.

AIN1–, AIN2– and AIN3– are inverting inputs for the op-amp.

GSX1, GX2 and GX3 are the outputs for op-amp.

Do the level adjustment as described below.

If AINn– and AINn+ are not used, connect AINn– to GSXn and AINn+ to SGC.

During power saving and power down modes, GSX1, GSX2, and GSX3 outputs are at a high impedance. During

power down mode in each channel, the GSX output of a channel in power down mode is at a high impedance.

Channel n

analog input

C1n R1n

GSXn

R2n

AINn–

AINn+

SGC

SG

Gen.

Channel n gain

Gain = R2n/R1n ≤ 10

R1: Variable

R2 > 20 kΩ

C1n > 1/(2 × 3.14 × 30 × R1n)

R1 + R2 < 500 kΩ

AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, AOUT3–

AOUT1+ and AOUT1– are the receive analog output pins for Channel 1, AOUT2+ and AOUT2– are those for

Channel 2, and AOUT3+ and AOUT3– are those for Channel 3.

AOUT1– is the inverting output for AOUT1+, AOUT2– is for AOUT2+, and AOUT3– is for AOUT3+. A load of

600Ω or more can be driven between AOUT1+ and AOUT1–, AOUT2+ and AOUT2–, and AOUT3+ and

AOUT3–. The output signal has an amplitude of 3.4 Vpp above and below the signal ground voltage (SG) when

the digital signal of 3.17 dBm0 is input to DIN1, DIN2, and DIN3.

During power saving and power down modes, the AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, and

AOUT3– outputs are at a high impedance.

During power down mode in each channel, the AOUTn+ and AOUTn– of a channel in power down are at a high

impedance.

SGC

Bypass capacitor pin used to generate the signal ground voltage level.

Connect a 1 µF capacitor with excellent high frequency characteristics between the SGC pin and the AG pin.

MCK

Master clock input pin. The frequency is 12.288 MHz or 15.360 MHz.

The frequency is switched by MCKSEL. This master clock may be asynchronous with BCLK, RSYNC, and

XSYNC.

MCKSEL

Master clock frequency select signal input pin. Input a 12.288 MHz clock to the MCK pin when MCKSEL is “0”.

Input a 15.360 MHz clock to the MCK pin when MCKSEL is “1”.

PDN

Power down control signal input pin. When PDN is “0”, all circuits are in power down mode.

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