ML7048 데이터 시트보기 (PDF) - Oki Electric Industry

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ML7048

3-Channel Single Rail CODEC

Oki Electric Industry 

1Semiconductor

PEDL7048-01-01

ML7048-01

PDN1, PDN2, PDN3

PDN1 is the power down control signal input pin for Channel 1, PDN2 is for Channel 2, and PDN3 is for Channel

3.

When PDN is “1” and PDN1, PDN2, and PDN3 are “0s”, the corresponding channel goes in power saving mode

(all analog circuits except the reference voltage generation circuit are being powered down).

P/S

Signal input pin for selecting either 3-channel independent serial interface or 3-channel continuous serial interface.

When P/S is “0”, 3-channel independent serial interface, in which the input/output of each channel is made through

DIN1 to 3 and DOUT1 to 3 independently, is selected.

When P/S is “1”, 3-channel continuous serial interface, in which the input/output of each channel is made from

DIN1 and DOUT1 continuously.

When 3-channel continuous serial interface is selected, DOUT2 and DOUT3 pins are at a high impedance.

Connect the DIN2 and DIN3 pins to the digital ground (DG).

BCLK

PCM signal shift clock input pin for DIN1, DIN2, DIN3, DOUT1, DOUT2, and DOUT3.

The frequency is equal to the data rate.

The clock frequencies available are 64, 96, 128, 192, 256, 384, 512, 1024, 1536, and 2048 kHz.

When P/S is “1” and 3-channel continuous serial interface is selected, the frequencies of 64, 96, and 128 kHz

cannot be used.

RSYNC

Receive synchronizing signal input pin.

This signal selects necessary 8-bit PCM data from serial PCM signals for the DIN1, DIN2 and DIN3 pins. This

synchronizing signal must be synchronized in phase with BCLK (generated from BCLK).

XSYNC

Transmit synchronizing signal input pin.

This synchronizing signal must be synchronized in phase with BCLK (generated from BCLK). The DPLL circuit

is synchronized in phase with XSYNC.

DIN1, DIN2, DIN3

When P/S is “0” and 3-channel independent serial interface is selected, DIN1 is the PCM signal input pin for

Channel 1, DIN2 is for Channel 2, and DIN3 is for Channel 3.

When P/S is “1” and 3-channel continuous serial interface is selected, DIN1 is the PCM signal input pin for each

channel and data is input in the order of Channel 1, Channel 2 and Channel 3.

At that time, connect DIN2 and DIN3 to the digital ground (DG).

The PCM signal data rate is equal to the frequency of BCLK. The PCM signal is shifted at the falling edge of

BCLK. The MSD of PCM data is identified at the rising edge of RSYNC.

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