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ML6652EM 데이터 시트보기 (PDF) - Micro Linear Corporation

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ML6652EM Datasheet PDF : 28 Pages
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ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
DUPLEX and SPEED can be used concurrently to set the power up mode of
the ML6652 see Tables 4 and 6. For Mode details see the General Description
section of this data sheet.
27
SPEED
I
This input can have one of three levels: VCC, VCC/2, and 0Volts. The input
has 80kresistors internally connected to both VCC and Ground generating
VCC/2 at the input, if left unconnected. Settings defined by the SPEED power
up preset pin can be over written by the management interface. At power up
the SPEED pin causes the following default values to be written to
management register 30.
Note: this pin is typically read a few microseconds after power-up. If it is tied
to supplies that do not track the ML6652 power, improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
SPEED Voltage
0
VCC/2
VCC
DSBLAN <30.14>
Default
1
0
1
SINGLESPEED <30.9>
Default
1
0
1
SEL10Mbps <30.8>
Default
1
0
0
Table 5.
Mode
Forced 10
Forced 100
Non-Transparent
Half-Duplex
Non-Transparent
Transparent
Operating Summary
SPEED Voltage
10Mbps data rate only available. The Duplex mode
0
is selected by the link partner.
100Mbps data rate only available. The Duplex mode
VCC
is selected by the link partner.
Only the Half-Duplex mode is advertised. Both 10
VCC/2
and 100Mbps data rates are available. Only the data
rate equivalent to the technology present at the fiber
optic input interface is advertised.
FLP Bursts are generated. Both Half-Duplex and
VCC/2
Full-Duplex modes are advertised. Both 10 and
100Mbps data rates are available. Only the data rate
equivalent to the technology present at the fiber optic
input interface is advertised.
Standard Auto-Negotiation sub-layer 10Mbps,
VCC/2
100Mbps and Auto-Negotiation far end link partner
signaling available.
DUPLEX Voltage
N/A
N/A
0
VCC
VCC/2
Table 6.
7
January 2004
Final Datasheet
DS6652-F-02

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