MM74HC139N 데이터 시트보기 (PDF) - Fairchild Semiconductor
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MM74HC139N Datasheet PDF : 8 Pages
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September 1983
Revised December 2003
MM74HC139
Dual 2-To-4 Line Decoder
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses the
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
The MM74HC139 contain two independent one-of-four
decoders each with a single active low enable input (G1, or
G2). Data on the select inputs (A1, and B1 or A2, and B2)
cause one of the four normally high outputs to go LOW.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally as well as pin
equivalent to the 74LS139. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
s Typical propagation delays —
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
s Low power: 40 µW quiescent supply power
s Fanout of 10 LS-TTL devices
s Input current maximum 1 µA, typical 10 pA
Ordering Code:
Order Number Package Number
Package Description
MM74HC139M
(Note 1)
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC139SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC139MTC
(Note 1)
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC139N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Inputs
Enable Select
G
BA
H
XX
L
LL
L
LH
L
HL
L
H = HIGH Level
L = LOW Level
X = Don't Care
HH
Outputs
Y0 Y1 Y2 Y3
HHHH
L HHH
H LHH
HH L H
HHHL
© 2003 Fairchild Semiconductor Corporation DS005311
www.fairchildsemi.com
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